Dylan Patel — Deep dive on the 3 big bottlenecks to scaling AI compute

AI compute growth is increasingly constrained not by headline hyperscaler spending, but by how far upstream the bottlenecks now sit in the semiconductor supply chain. Dylan Patel’s central claim is that the often-cited 2026 capex figures—roughly $600 billion across Amazon, Meta, Google, and Microsoft, and close to $1 trillion across the broader supply chain—should not be interpreted as compute coming online immediately. A large share is advance work: turbine deposits for 2028-29, data-center shells for 2027, land, power contracts, and other enabling infrastructure. On his numbers, the U.S. adds about 20 GW of incremental AI data-center capacity this year, while labs like Anthropic and OpenAI are already pushing against much larger future needs. Patel argues Anthropic in particular was too conservative about contracting for compute; because its revenue accelerated faster than expected, it now needs to scramble for capacity from lower-quality or more expensive providers, often through revenue-sharing arrangements with hyperscalers or through short-term spot-like deals.

That near-term scramble leads into Patel’s broader economic argument: in a supply-constrained world, compute committed early becomes a major competitive advantage. He cited H100 deals at up to $2.40 per GPU-hour for 2-3 years against a roughly $1.40/hour five-year deployed cost base, implying large supplier margins and sharp penalties for late buyers. This also changes the GPU depreciation debate. A bearish view says older GPUs should collapse in value as new chips deliver better performance per dollar. Patel’s rebuttal is that when new chips are themselves supply-constrained, the market prices older GPUs by their current utility, not by a neat benchmark-relative depreciation curve. If a newer model architecture can extract more useful output from the same H100 fleet than prior software generations could, the economic value of that installed base can rise rather than fall. In that framing, compute reservations function almost like long-dated options on future AI capability and revenue.

From there the conversation shifts to the “three big bottlenecks”: logic, memory, and the tools that make both. Patel’s most concrete claim is that by 2028-30 the ultimate limiter is ASML’s EUV lithography output. He walks through the arithmetic for 1 GW of Nvidia Rubin-class compute: about 55,000 3nm wafers, 6,000 5nm wafers, and 170,000 DRAM wafers, together requiring roughly 2 million EUV wafer passes, or about 3.5 EUV tools’ worth of capacity. Since ASML may only reach a bit above 100 EUV tools shipped per year by 2030, even aggressive AI buildouts eventually run into a hard manufacturing ceiling. The deeper point is that the key supply chains are extremely slow to expand. Fabs take 2-3 years to build; EUV tools are assembled from hyper-specialized subcomponents such as Carl Zeiss optics, wafer stages, and laser-produced plasma sources; and each expansion step requires scarce talent and precise industrial coordination. Patel repeatedly contrasts this with power and data centers, which, though difficult, are far simpler and faster to scale.

Memory is the second major pressure point, and Patel portrays it as both an AI and consumer-electronics story. He argues that HBM’s economics are brutal because it consumes 3-4x more DRAM wafer area per bit than commodity memory, yet AI accelerators need HBM because bandwidth, not just capacity, is often the real constraint. He quantifies HBM4 at about 2.5 TB/s per stack, versus only 64-128 GB/s for DDR5 over similar edge area, making “just use commodity DRAM” a poor substitute. The result is that roughly a third of 2026 big-tech AI capex may effectively be going to memory, while DRAM and NAND price increases ripple into phones and PCs. Patel predicts higher iPhone BOMs, falling low-end smartphone production, and broader consumer frustration as AI absorbs supply that once fed mass-market electronics. Here the speakers largely agree, though Dwarkesh pushes on whether slower, lower-bandwidth models could open a different hardware design point; Patel’s answer is that the market will still allocate scarce compute toward the highest-value, least price-sensitive uses.

On infrastructure beyond chips, Patel is strikingly bullish that power can be solved and skeptical that space data centers are relevant this decade. He thinks there are many more viable generation pathways than investors appreciate—combined-cycle turbines, aeroderivatives, reciprocating engines, ship engines, Bloom fuel cells, batteries, and renewables paired with storage—and that permitting and labor are serious but tractable relative to semiconductor constraints. Space, by contrast, still uses the same scarce chips while worsening deployment time, networking topology, cooling, and maintenance. The final geopolitical layer is that Taiwan remains an irreplaceable concentration of know-how and capacity. Patel thinks China will likely indigenize DUV and perhaps demonstrate EUV by 2030, but not produce it at ASML scale by then. His bottom-line strategic view is nuanced: if AI progress and monetization continue compounding quickly, the U.S. benefits from already having the leading labs, capital base, and compute buildout; if timelines stretch toward 2035, China’s efforts to vertically integrate semiconductor production become more threatening. In other words, the shape of AI progress determines not just which bottleneck matters, but which country benefits from surviving it.